An FPGA-Based Heterogeneous Acceleration System for SM4 Algorithm

doi:10.3969/j.issn.1671-1122.2025.07.002

Abstract

Abstract:

The national cryptographic SM4 algorithm is widely used in the WAPI wireless network standard. Currently, the SM4 encryption-decryption research mainly focuses on the optimization of the hardware implementation structure to improve throughput and security. Meanwhile, the development of big data and 5G communication technology has raised higher requirements for the bandwidth and real-time performance of data encryption. Based on the background, this paper proposed an FPGA-based heterogeneous acceleration system for SM4 algorithm, which used hardware to implement the SM4 algorithm and optimize encryption performance. The system adopted a streaming high-speed data transmission architecture, supported multiple SM4 cores to work in parallel, and fully utilized the computer bandwidth. The system was designed with configurable interfaces to connect SM4 with the transmission architecture and provided sufficient flexibility. The system was implemented on Xilinx XCVU9P FPGA and supported changing the load and mode of SM4 anytime. Through experiments, the maximum operating frequency of SM4 is 462MHz, the system throughput is as high as 92Gbit/s, and the delay is only 266μs. The results show that compared with other existing works, this system can achieve higher SM4 operating frequency and system throughput, which meets the high bandwidth and low latency requirements of SM4 acceleration.

Key words: SM4 algorithm, FPGA, hardware acceleration, transmission architecture

CLC Number:

TP309

ZHANG Quanxin, LI Ke, SHAO Yujie, TAN Yu’an. An FPGA-Based Heterogeneous Acceleration System for SM4 Algorithm[J]. Netinfo Security, 2025, 25(7): 1021-1031.

Figures/Tables 13

References 23

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方案	资源消耗	运行频率/MHz	吞吐量/Gbit·s^-1	硬件设备
文献[19]	8373 ALM	162	20.74	StraitxⅡ
文献[20]	9500 SLICE	190	24.32	Virtex-4
文献[21]	7667 LUT, 5438 FF	212	27.15	StraitxⅣ
文献[15]	3213 LUT, 7736 FF, 33 BRAM	344	42.10	Kintex-7
本文	19608 LUT, 48866 FF	462	59.14	Virtex UltraScale

方案	速率/Gbit·s^-1	硬件设备
OpenSSL	1.3	Intel Core i7-11800H@2.3 GHz
DMCrypt	1.1	Intel Core i9-11900F @2.50 GHz
文献[4]	2.4	Intel Core i7-6700@3.40 GHz
文献[5]	2.5	Intel Core i7-7700HQ（Kabylake）@2.80 GHz
文献[6]	6.7	Intel Core i7-11800H@2.3 GHz
本文	92（多核）	Virtex UltraScale
本文	59（单核）	Virtex UltraScale

方案	PCIE	速率/Gbit·s^-1	硬件设备
文献[17]	3.0	0.785	Virtex UltraScale
文献[18]	2.0×4	13.53	—
文献[23]	—	0.013	Altera Cyclone II
本文	3.0×16	92（多核）	Virtex UltraScale
本文	3.0×16	59（单核）	Virtex UltraScale