Abstract:

Matrix-vector multiplication is the main computational bottleneck of lattice-based Post-Quantum Cryptography (PQC) schemes. Utilizing the number theoretic transform (NTT) can reduce the computational complexity of matrix-vector multiplication from O(N²) to O(Nlog₂N), thereby further improving the computational speed of post-quantum cryptographic schemes. This article proposed an area-efficient dual-mode configurable NTT hardware accelerator based on field programmable gate array (FPGA), capable of efficiently executing NTT operations in the Kyber and Dilithium algorithms. The multiplier used in the proposed design compresses data bit width and reduced modulo costs using table lookup techniques, followed by reduction of results using the KRED algorithm. Furthermore, by combining optimized non-conflicting NTT data streams, the proposed dual-mode configurable NTT accelerator can efficiently complete computations. The NTT hardware accelerator proposed in this article is validated on the Xilinx Artix-7 platform. Compared to the reference work, the proposed dual-mode configurable NTT hardware accelerator performs better in terms of computational performance and hardware overhead while maintaining generality for Kyber and Dilithium algorithms.

Key words: post-quantum cryptography, number theoretic transform, modular multiplication, hardware acceleration, field programmable gate array