Design of High Speed Reconfigurable Modulo Arithmetic Unit for Block Cipher

doi:10.3969/j.issn.1671-1122.2023.05.008

Abstract

Abstract:

Modulo arithmetic unit is the key component of coarse grain reconfigurable cryptographic array (CGRCA). It can cover more types of block ciphers by reconfiguring arithmetic cryptographic operators with different processing width and modulus. However, the high execution latency and low functional coverage of the existing modulo arithmetic units limit the overall performance improvement of CGRCA. By analyzing the characteristics of modulo arithmetic in block ciphers, this paper proposed reconfigurable modular arithmetic unit (RMAU), which unified the mathematical expression of the operators and designed a RMAU. The unit supported five modular multiplication operations, three modular addition operations, and three multiply-accumulate operations. At the same time, the critical path delay of the unit was optimized by discarding useless bits in the partial product, extending the Wallace tree to compress the summing process, and shortening the modular correction module’s execution path. The function and performance of RMAU were tested in CMOS 180 nm process. The experimental results show that while RMAU has high functional coverage, compared with modular multiplier RCE unit, extensible modular multiplier structure and RNS multiplier, the computation delay is reduced by 39%, 44% and 47%, respectively.

Key words: reconfigurable computing, modular multiplication, block cipher, modulo correction operation

CLC Number:

TP309

ZHANG Xiaolei, DAI Zibin, LIU Yanjiang, QU Tongzhou. Design of High Speed Reconfigurable Modulo Arithmetic Unit for Block Cipher[J]. Netinfo Security, 2023, 23(5): 76-84.

Figures/Tables 11

References 21

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模运算类型	模数	算法	算法数量
模加运算	2⁸	SAFER K、SAFER+、FEAL、HIGHT	4
	2¹⁶	IDEA、RC2、SAFER++	3
	2³²	Blowfish、MARS、CAST-128、CAST-256、GOST、WAKE、WiderWake、RC5、RC6、Twofish	10
模乘运算	2¹⁶	MESH	1
	2³²	MARS、RC6、E2、Twofish、Serpent、MultiSwap、Cipherunicorn-A	7
	2¹⁶+1	IDEA	1
	2³²-1	MMB	1

X₂_i₊₁	X₂_i	X₂_i_-1	X1b	X2b	Neg
0	0	0	1	1	0
0	0	1	0	1	0
0	1	0	0	1	0
0	1	1	1	0	0
1	0	0	1	0	1
1	0	1	0	1	1
1	1	0	0	1	1
1	1	1	1	1	1

乘法器	延迟/ns	面积/μm²	功耗-延迟积/ （ns·μm²）	工艺/nm	支持算法
模乘RCE单元^[19]	4.62	127260	587941	180	模2¹⁶乘法、模2¹⁶+1乘法、模2³²乘法、模2³²-1乘法
高速可重构乘法器^[4]	2.80	182752	511705.6	180	16 bit乘法、32 bit乘法、模2¹⁶乘法、模2¹⁶+1乘法
可扩展模乘结构^[20]	5.00	-	-	180	32 bit乘法、模2¹⁶+1乘法、模2³²+1乘法
PE阵列^[21]	1.27	1585	2012.95	40	模2⁸加法、模2¹⁶加法、模2³²加法
RNS乘法器^[5]	5.28	61661	325570.08	180	模2¹⁶+1乘法、模2¹⁶-1乘法
RMAU	1.17	11778	13780.26	40	模2⁸乘法、模2¹⁶乘法、模2³²乘法、8比特乘法、16比特乘法模2⁸加法、模2¹⁶加法、模2³²加法模2⁸乘法、模2¹⁶乘法、模2³²乘法模2¹⁶+1乘法、模2³²+1乘法、乘法累加运算
RMAU	2.80	86765	242942	180