Endogenous Secure Microcontroller Design and Implementation

doi:10.3969/j.issn.1671-1122.2025.03.005

Abstract

Abstract:

In response to the problem that microcontrollers were currently unable to prevent the security threats brought by unknown vulnerabilities and unknown backdoors, the paper first proposed a microcontroller architecture based on dynamic heterogeneous redundancy, grounded in the theory of intrinsic security. Secondly, to overcome the performance bottlenecks caused by the arbitration of dynamic heterogeneous redundancy architecture and to meet the low latency requirements of microcontroller applications, an arbitration output method was proposed to enhance the system’s real-time capabilities, reducing system response latency without compromising system security. In addition, a prototype system of the intrinsically secure microcontroller was designed and implemented, and the system’s security and response latency metrics were tested. The test results indicate that the realized intrinsically secure microcontroller system has higher precision in identifying system attacks, and can reduce the response time by up to 13.78% compared to the traditional method of arbitration before output.

Key words: microcontroller, endogenous security, dynamic heterogeneous redundancy, arbitration and scheduling

CLC Number:

TP309

YU Hong, LAN Julong, OUYANG Ling. Endogenous Secure Microcontroller Design and Implementation[J]. Netinfo Security, 2025, 25(3): 415-424.

Figures/Tables 13

符号	定义
${{E}_{i}}.tot\_corr$	执行体 ${{E}_{i}}$ 总判决正确次数
${{E}_{i}}.tot\_incorr$	执行体 ${{E}_{i}}$ 总判决错误次数
${{E}_{i}}.rec\_corr$	执行体 ${{E}_{i}}$ 最近判决正确次数
${{E}_{i}}.rec\_incorr$	执行体 ${{E}_{i}}$ 最近判决错误次数
${{E}_{i}}.duration$	执行体 ${{E}_{i}}$ 在上次调度后持续工作时间
${{E}_{i}}.fst\_arr$	执行体 ${{E}_{i}}$ 第一次到达裁决模块次数
${{E}_{i}}.snd\_arr$	执行体 ${{E}_{i}}$ 第二次到达裁决模块次数
${{E}_{i}}.trd\_arr$	执行体 ${{E}_{i}}$ 第三次到达裁决模块次数
${{E}_{i}}.cur\_stat$	执行体 ${{E}_{i}}$ 当前状态（工作/调度中）
${{E}_{i}}.is\_twin$	是否存在其他执行体与执行体 ${{E}_{i}}$ 输出相同
${{E}_{i}}.eql\_output$	执行体 ${{E}_{i}}$ 这一轮的输出是否与系统输出一致

符号	定义
$\lambda$	单位时间内裁决输出的次数
${{\theta }_{i}}$	执行体 ${{E}_{i}}$ 实际受攻击概率
${{\rho }_{i}}$	执行体 ${{E}_{i}}$ 实际处理数据平均开销
${{t}_{str}}$	裁决器数据直通输出时间开销
${{t}_{arb}}$	裁决器数据裁决输出时间开销
${{t}_{s}}$	数据直通输出总时间开销
${{t}_{a}}$	数据裁决输出总时间开销
${{t}_{sche}}$	执行体调度时间开销
$\psi$	单次响应中数据直通与数据裁决时间开销比
$\chi$	裁决算法错误率
$\mu$	主通道选择算法准确率
$\eta$	安全度计算算法准确率

参数	设置
查询总数	10000
${{E}_{1}}$ 插桩次数	1000
${{E}_{2}}$ 插桩次数	500
${{E}_{3}}$ 插桩次数	200
${{E}_{1}}$ 、 ${{E}_{2}}$ 同时非协同攻击次数	50
${{E}_{1}}$ 、 ${{E}_{2}}$ 协同攻击次数	20
${{E}_{1}}$ 、 ${{E}_{3}}$ 同时非协同攻击次数	20
${{E}_{1}}$ 、 ${{E}_{3}}$ 协同攻击次数	10
${{E}_{2}}$ 、 ${{E}_{3}}$ 同时非协同攻击次数	10
${{E}_{2}}$ 、 ${{E}_{3}}$ 协同攻击次数	5
${{E}_{1}}$ 、 ${{E}_{2}}$ 、 ${{E}_{3}}$ 同时非协同攻击次数	5
${{E}_{1}}$ 、 ${{E}_{2}}$ 、 ${{E}_{3}}$ 协同攻击次数	2
随机调度周期	10

执行体	方法	TP	FN	TN	FP	F1_measure	同比增加	总异常	总错判
${{E}_{1}}$	MMA	1175	54	8691	80	0.9460	—	1255	134
${{E}_{2}}$		660	44	9226	70	0.9205	—	730	114
${{E}_{3}}$		285	94	9571	50	0.7983	—	335	144
${{E}_{1}}$	ERTA	1105	15	8830	50	0.9714	2.68%	1155	65
${{E}_{2}}$		672	30	9243	55	0.9405	2.17%	727	85
${{E}_{3}}$		274	20	9636	70	0.8589	7.59%	344	90

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威胁情况	调度周期
1个执行体受攻击	经历1轮调度
2个执行体受非协同攻击	经历2轮或3轮调度
2个执行体受协同攻击	经历3轮调度
3个执行体受攻击	经历3轮调度