基于FPGA的FESH分组密码算法高速实现

doi:10.3969/j.issn.1671-1122.2021.01.007

信息网络安全 ›› 2021, Vol. 21 ›› Issue (1): 57-64.doi: 10.3969/j.issn.1671-1122.2021.01.007

基于FPGA的FESH分组密码算法高速实现

王建新¹, 周世强¹, 肖超恩¹(), 张磊¹^,²

1.北京电子科技学院电子与通信工程系,北京 100070
2.北京工商大学农产品质量安全追溯技术及应用国家工程实验室,北京 100048

收稿日期:2020-11-24 出版日期:2021-01-10 发布日期:2021-02-23
通讯作者: 肖超恩 E-mail:xce@besti.edu.cn
作者简介:王建新（1977—）,男,河北,副教授,博士,主要研究方向为信息安全|周世强（1996—）,男,湖北,硕士研究生,主要研究方向为信息安全|肖超恩（1982—）,男,湖南,讲师,博士,主要研究方向为信息安全|张磊（1979—）,男,河北,教授,博士,主要研究方向为信息安全
基金资助:
国家重点研发计划(2017YFB0801803);农产品质量安全追溯技术及应用国家工程实验室开放课题(AQT-2018-YB5)

High-speed Implementation of FESH Block Cipher Algorithm Based on FPGA

WANG Jianxin¹, ZHOU Shiqiang¹, XIAO Chaoen¹(), ZHANG Lei¹^,²

1. Department of Electronic and Communication Engineering, Beijing Electronics Science and Technology Institute, Beijing 100070, China
2. National Engineering Laboratory for Agri-product Quality Traceability, Beijing Technology and Business University, Beijing 100048, China

Received:2020-11-24 Online:2021-01-10 Published:2021-02-23
Contact: XIAO Chaoen E-mail:xce@besti.edu.cn

摘要/Abstract

摘要：

FESH分组密码算法为2019年全国密码算法竞赛中进入第二轮评选的密码算法。文章对该算法的FESH-128-128型进行Verilog HDL高速实现,在有限状态机的基础上对顶层模块采用流水线设计方法进行优化,通过寄存器存储中间数据,提高运行效率。实验结果表明,在软件Quartus II 15.0上使用5CEFA7F31C6芯片进行综合设计,采用流水线设计方法进行优化后,算法最高运行速率达到296.74 MHz,相较于有限状态机实现提高了98.28%;吞吐率达到37.98 Gbps,相较于有限状态机实现提升了约33倍。

关键词: FESH, 分组密码, Verilog HDL高速实现, 流水线设计

Abstract:

The FESH block cipher algorithm is the cipher algorithm that entered the second round of selection in the 2019 national encryption algorithm competition. In this paper, the FESH-128-128 type of the algorithm is implemented in Verilog HDL at a high speed. On the basis of the finite state machine, the top-level module adopts the pipeline design method to optimize, and the intermediate data is stored in the register to improve the operating efficiency. The results show that the 5CEFA7F31C6 chip is used for synthesis on the software Quartus II 15.0, and the pipeline design method is used to optimize the maximum operating speed of 296.74 MHz, which is 98.28% higher than the finite state machine implementation; the throughput rate reaches 37.98 Gbps, which Compared with the finite state machine, the realization is improved by about 33 times.

Key words: FESH, block cipher, high-speed implementation of Verilog HDL, pipeline design

中图分类号:

TP309

王建新, 周世强, 肖超恩, 张磊. 基于FPGA的FESH分组密码算法高速实现[J]. 信息网络安全, 2021, 21(1): 57-64.

WANG Jianxin, ZHOU Shiqiang, XIAO Chaoen, ZHANG Lei. High-speed Implementation of FESH Block Cipher Algorithm Based on FPGA[J]. Netinfo Security, 2021, 21(1): 57-64.

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端口名称	端口宽度/bit	描述
clock	1	时钟输入
reset	1	判断位输入
datain	128	明文输入
codein	128	密钥输入
dataout	128	密文输出

	有限状态机设计	流水线设计	提升率%
接口/个	386	385	-0.26
逻辑单元/个	4075	5068	24.36
寄存器/个	18	8524	47255.56
最高工作频率/MHz	149.66	296.74	98.28

基于FPGA的FESH分组密码算法高速实现

High-speed Implementation of FESH Block Cipher Algorithm Based on FPGA

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参考文献 30

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算法	分组长度（n）/bit	密钥长度（m）/bit	轮数（N）
FESH-128-128	128	128	16
FESH-128-192	128	192	20
FESH-128-256	128	256	20
FESH-256-256	256	256	24
FESH-256-384	256	384	28
FESH-256-512	256	512	28

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