Abstract: Hardware Trojan is a malicious circuit which is so tiny and covert, masking in the chip to modify the inputs and outputs’ nodes status or function of the target chip. With the increasing globalization of the design and fabrication of integrated circuits(ICs), it makes the chips easier to be inserted Hardware Trojans due to the separation of the design and production processes, which leads to the huge threat of the ICs’ security and reliability. How to detect whether the test chip containing the Hardware Trojan to ensure safety of the integrated circuits is becoming more and more important. The authors designed a kind of theft-type Hardware Trojan in the netlist of the AES encryption algorithm based on 40-nm standard cell libraries, and the size of the Hardware Trojan was about 2.7% compared with the Golden pure AES circuit (Trojan-free), then the design was analyzed through different operating voltages of the parameter of the PVT (process & voltage & temperature), which caused the different laws of the side-channel power consumption, we have found that the verification of the side-channel power consumption caused by the implanting Hardware Trojan could be overwhelmed by the working voltage jitter, so that reduced the Hardware Trojan detection efficiency. Based on the article, we present a method to manifest the side-channel power consumption of the Hardware Trojan based on the random scanning voltage, which circumvent the effects of the verification of side-channel power consumption due to the voltage fluctuation in the normal Hardware Trojan detection, and achieve the goal of the Hardware Trojan’s detection.